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    • 专利摘要:
    The invention relates to a memory circuit adapted to implement calculation operations, comprising: memory cells (10i, j) arranged in rows and columns, each cell comprising: a node (BLTI) for storing a bit of data, - a read transistor (T3) connected by its gate to the storage node (BLTI), and - a selection transistor (T4) in series with the read transistor (T3) between a node (VGNDT) of reference and an output conductive track (RBLT) common to all the cells of the same column; and a control circuit (14) configured to simultaneously activate the selection transistors (T4) of at least two cells (10i, j, 10i + 1, j) of a same column, and to read on the conductive track of output (RBLT) of the column a value representative of the result of a logical operation whose operands the data of the two cells (10i, j, 10i + 1, j).
    公开号:FR3051960A1
    申请号:FR1654623
    申请日:2016-05-24
    公开日:2017-12-01
    发明作者:Jean-Philippe Noel；Kaya Can Akyel
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    MEMORY CIRCUIT SUITABLE FOR IMPLEMENTING OPERATIONS OF
    CALCULATION
    Field
    The present application relates to the field of digital computing circuits.
    Presentation of the prior art
    In a conventional manner, a digital calculation circuit, for example a microprocessor, comprises an internal memory (bank of registers, cache memory, etc.), and an arithmetic and logic unit (ALU) adapted to implement arithmetic operations and / or or basic logic for processing data contained in the internal memory of the circuit.
    A limitation to the increase in the operating speed of the digital computing circuits is related to the operating speed of the internal memory, which does not follow the same increase as that of the arithmetic and logic unit.
    Another limitation of the existing architectures is related to the large length of the conductive routing tracks connecting the internal memory to the arithmetic and logic unit, which causes significant energy consumption and high heat dissipation at each data transfer between the memory internal and the arithmetic and logical unit. summary
    Thus, an embodiment provides a memory circuit adapted to implement calculation operations, this circuit comprising: a plurality of elementary memory cells arranged according to lines and columns, each cell comprising: a first storage node of a data bit, - a first sense transistor connected by its gate to said first storage node, and - a first selection transistor connected in series with the first sense transistor between a first application node of a reference potential. the cell and a first output conductive track common to all the cells of the same column of the circuit; and a control circuit configured to simultaneously activate the first selection transistors of at least two cells of the same column of the circuit, and to read on the first conductive output track of the column a value representative of the result of a first logic operation having for operands the data stored in said at least two cells.
    According to one embodiment, the memory circuit further comprises, for each column of the circuit, a first inverter of which an input node is connected to the first conductive output track of the column.
    According to one embodiment, each elementary cell further comprises: a second storage node of a data bit complementary to the bit stored on the first storage node of the cell; a second reading transistor connected by its gate to said second storage node, and a second selection transistor connected in series with the second reading transistor between a second application node of a reference potential of the cell and a second output conduction track common to all the cells of the cell. a same column of the circuit, the control circuit being further configured to simultaneously activate the second selection transistors of at least two cells of the same column of the circuit, and to read on the second conductive output track of the column a value representative of the result of a second logical operation having for operands the data stored in said at least two cells.
    According to one embodiment, the control circuit is further configured to simultaneously activate: the first and second selection transistors of two cells of the same column of the circuit; or the first selection transistor of a first cell of the circuit and the second selection transistor of a second cell of the same column.
    According to one embodiment, the memory circuit further comprises, for each column of the circuit, a second inverter whose input node is connected to the second conductive output track of the column.
    According to one embodiment, the memory circuit further comprises, for each column of the circuit, a NOR logic gate whose first input is connected to the first conductive output track of the column and a second input of which is connected to the second conducting track output of the column.
    According to one embodiment, the memory circuit furthermore comprises, for each column of the circuit, a first NAND logic gate whose first input is connected to an output node of the NOR logic gate of the column, and a second gate and a first input is connected to an output node of the first logic gate AND of the column and a second input of which is connected to the second conductive output track of the column.
    According to one embodiment, in each column except for the first column of the circuit, the first NAND logic gate has a second input connected to the second output conductor track of a previous rank column of the circuit.
    According to one embodiment, the memory circuit further comprises, for each column: a first reference conductive track interconnecting the first reference potential application nodes of the column; and a second reference conductive track interconnecting the second reference potential application nodes of the column.
    According to one embodiment, the memory circuit further comprises, for each column: a first reference transistor connecting the first reference conductor track to a reference node; and a second reference transistor connecting the second reference conducting track to said reference node.
    According to one embodiment, the memory circuit further comprises, for each column, an AND gate, an OR logic gate, and third, fourth, fifth and sixth inverters, and: the AND logic gate has a first input connected to an application node of a first control bit signal via the third inverter, and a second input connected to an application node of a second control bit signal via the fourth inverter / output the third inverter is connected to the first reference conductor track of the column via the fifth inverter; the OR logic gate has a first input connected to the first conductive output track of the column, and a second input connected to the output of the AND logic gate; and the output of the OR logic gate is connected to the second reference conductive track of the column via the sixth inverter.
    According to one embodiment, the memory circuit further comprises, for each column of the circuit: a first multiplexer having a first input connected to the input of the first inverter and a second input connected to the output of the first inverter / a third inverter whose the input is connected to the output of the first multiplexer / a third NAND gate, a first input of which is connected to the output of the first multiplexer and a second input of which is connected to the input of the second inverter / a fourth NAND gate of which a first input is connected to the output of the third inverter and a second input is connected to the output of the second inverter; and a fifth NAND gate having a first input connected to the output of the third NAND gate and whose output is connected to the output of the fourth NAND gate.
    According to one embodiment, the elementary memory cells are volatile memory cells of the SRAM type.
    According to one embodiment, the elementary memory cells are non-volatile resistive memory cells. Brief description of the drawings
    These features and their advantages, as well as others, will be set forth in detail in the following description of particular embodiments in a nonlimiting manner in connection with the accompanying figures, in which: FIG. 1 is an electrical diagram of an example a memory circuit according to one embodiment; Figure 2 schematically shows an example of a memory circuit according to one embodiment; FIG. 3 schematically represents an alternative embodiment of the memory circuit of FIG. 2; Figure 4 schematically shows another variant of a memory circuit according to one embodiment; Figure 5 schematically shows another example of a memory circuit according to one embodiment; FIG. 6 schematically represents an alternative embodiment of the memory circuit of FIG. 5; FIG. 7 schematically represents another variant embodiment of the memory circuit of FIG. 5; and Fig. 8 is a circuit diagram of another example of an elementary cell of a memory circuit according to one embodiment.
    detailed description
    The same elements have been designated with the same references in the various figures. For the sake of clarity, only the elements that are useful for understanding the described embodiments have been shown and are detailed. In the following description, the references to high and low level signals must be interpreted in a relative manner, as corresponding to two distinct states of the binary signals processed by the circuits described. By way of example, the high level signals correspond to potentials of the order of a high VDD supply potential of the circuits described (for example equal to λ / DD at 0.5λ / close), and the Low level signals correspond to potentials of the order of a low supply potential GND of the circuits described (for example equal to GND at 0.5λ / close).
    According to one aspect of the described embodiments, there is provided a memory circuit adapted not only to store data, but also to perform, in-situ, when accessing the contents of the memory, a certain number of logical operations and / or arithmetic whose operands are data stored in the circuit. The results of the calculations can be transmitted to circuits external to the memory, and / or be rewritten in the memory.
    Figure 1 is an electrical diagram of an example of an elementary cell 10 of a memory circuit according to one embodiment.
    The elementary cell 10 of FIG. 1 is a ten transistor cell. It comprises a SRAM 12 storage cell with six transistors, and two RPT and RPF read ports with two transistors each. The storage cell 12 comprises two inverters (two transistors each) mounted in antiparallel between a first node BLTI for storing a data bit, and a second node BLFI for storing a bit of data complementary to the bit stored on the node. BLTI. The storage cell 12 furthermore comprises a first write access transistor T1, connecting the BLTI node to a write conductive trace WBLT by its conduction nodes, and a second write access transistor T2 connecting, by its conduction nodes the BLFI node to a write conductive track WBLF. The gates of the transistors T1 and T2 are connected to the same write control conductor track WWL. The read port RPT comprises two transistors T3 and T4 connected in series via their conduction nodes between a conductive track VGNDT for applying a reference potential and an output conducting track RBLT. The transistor T3 is located on the trackside VGNDT and has its gate connected to the node BLTI, and the transistor T4 is located RBLT trackside and has its gate connected to a RWLT read control conductive track. The RPF read port comprises two transistors T5 and T6 connected in series via their conduction nodes between a conductive track VGNDF for applying a reference potential and an output conducting track RBLF. The transistor T5 is located on the VGNDF track side and has its gate connected to the BLFI node, and the transistor T6 is located on the RBLF side and has its gate connected to a RWLF read control conductive track. In this example, the transistors T1, T2, T3, T4, T5, T6 are N-channel MOS transistors.
    A memory circuit according to one embodiment comprises a plurality of elementary cells 10 of the type described in relation to FIG. 1, identical or similar, arranged in a matrix according to rows and columns. The cells of the same line are interconnected via their conductive tracks WWL, respectively RWLF, respectively RWLT, and the cells of the same column are interconnected via their conductive tracks RBLT, respectively VGNDT, respectively WBLT, respectively WBLF, respectively VGNDF, respectively RBLF. In other words, the cells of one and the same line share the same conducting track WWL, the same conducting track RWLF, and the same conducting track RWLT, and the cells of one and the same column share the same conducting track RBLT, the same one conductive track VGNDT, the same conductive track WBLT, the same conductive track WBLF, the same conductive track VGNDF, and the same conductive track RBLF. The distinct line cells have respective conductive tracks WWL, RWLF and RWLT, respectively, and the separate column cells have respective RBLT, respectively VGNDT, respectively WBLT, respectively WBLF, VGNDF or RBLF conductive tracks. .
    To perform a reading of an elementary cell 10 of the memory via its read port RPT, the output conductive track RBLT of the cell is precharged to a high level, for example to the supply voltage VDD of the circuit. The VGNDT conductive track is maintained at a low level, for example at the low GND potential with respect to which is referenced the supply voltage VDD of the circuit. The transistor T4 of the cell is then turned on by applying a high level signal on the conducting track RWLT of the cell. After the activation of the transistor T4, the conducting track RBLT discharges if the potential of the node BLTI is at a high level (passing transistor T3), and remains substantially at its precharging level if the potential BLTI is at a low level (transistor T3 blocked). The reading of the potential of the RBLT track via a not shown reading circuit, for example arranged at the bottom of the column, makes it possible to determine the value of the data bit stored in the elementary cell. The cell can also be read in substantially the same way via its RPF read port.
    FIG. 2 schematically represents an example of an embodiment of a memory circuit suitable for carrying out calculation operations. For the sake of simplification, only two elementary cells 10i, j and 10j + 1 of a same column of the memory circuit have been represented in FIG. 2, where i and j are indices designating respectively the rank of the line to which belongs the cell and the rank of the column to which the cell belongs, with i integer ranging from 1 to M and j integer ranging from 1 to N, M and N being integers respectively designating the number of rows and the number of columns of the memory circuit. In addition, the storage cells 12 of the elementary cells have not been detailed in FIG. 2.
    The memory circuit of FIG. 2 comprises a control circuit 14 (CTRL). The control circuit 14 is adapted to control the memory circuit to implement conventional read operations of the type described in connection with FIG. 1, or to implement write operations via the write access conductive tracks. WBLT, WBLF, and WWL cells.
    According to one aspect of an embodiment, the control circuit 14 is further adapted to control the memory circuit to implement calculation operations. For this purpose, the control circuit 14 is adapted to activate simultaneously two or more than two readings of elementary cells of the same column of the circuit, via the access ports RPT, and / or via the ports d RPF access of these cells. By way of illustrative example, it is considered that the two cells 10y and 10j shown in FIG. 2 are simultaneously activated for reading via their ports RPT and RPF. For this, after having preloaded at a high level the conductive output tracks RBLT and RBLF of the column and set at a low level the reference conductive tracks VGNDT and VGNDF of the column, the selection transistors T4 and T6 of the two cells 10i , j and 10i + i, j are simultaneously passed through the control circuit 14, via the RWLT and RWLF control conductive tracks of the lines 10l, j and 10j + 1. A denotes the binary value stored on the node BLTI of the cell 10y ^ j and B the binary value stored on the node BLTI of the cell 10j _ +] _ ^ j. The cell 10 1 then stores on its node BLFI the complementary A of the value A, and the cell 10 1 + 2 stores on its node BLFI the complementary B of the value B. The conductive output track RBLT of the column remains at its high precharge level only if both A and B values are at a low level. Thus, the level read on the output track RBLT of the column at the end of the read operation corresponds to the result A + B of a NOR logical calculation operation between the two selected memory cells. In addition, the output conductive track RBLF of the column remains at its high precharge level only if both values A and B are at a high level. Thus, the level read on the output track RBLF of the column at the end of the read operation corresponds to the result A.B of a logical calculation operation AND between the two selected memory cells.
    In the example of FIG. 2, the memory circuit further comprises, for each column of the matrix, for example arranged at the foot of the column, an inverter 16 whose input is connected to the output conductive track RBLT of the column , and an inverter 18 whose input is connected to the output conductive track RBLF of the column. Thus, at the end of a read operation of the type described above, the level read on the output node RBLT of the inverter 16 corresponds to the result A + B of a logic calculation operation OR between the two cells. selected memories, and the level read on the output node RBLF of the inverter 18 corresponds to the result AB of a logic calculation operation NOT AND between the two selected memory cells.
    Furthermore, in the example of FIG. 2, the memory circuit further comprises, for each column of the matrix, for example arranged at the foot of the column, a logic gate NOR or two with two inputs and an output, the inputs of the gate 20 being connected respectively to the RBLT track and the RBLF track. At the end of a read operation of the type described above, the level read at the output of the gate 20 corresponds to the result of a logical calculation operation NOT OR between the values A + B and AB, that is, that is, the XOR result (A, B) of an EXCLUSIVE OR logic calculation operation between the two selected memory cells.
    By simultaneously activating in read mode a number greater than two of cells of the same column, the aforementioned logic operations can be implemented with a number of operands greater than 2. Moreover, by simultaneously activating several columns of the circuit in read mode, these logical operations can be implemented on words of several bits.
    An advantage of the memory circuit of FIG. 2 is that it makes it possible to implement basic logic operations directly in the memory, without having to pass the data through an arithmetic and logic unit external to the circuit.
    This reduces the consumption and the dissipation of electrical energy related to the transfer of data between the memory and the arithmetic and logical unit.
    In addition, this makes it possible to increase the speed of execution of the calculations. Indeed, in a conventional architecture comprising an arithmetic and logic unit external to the memory, the execution of a logical calculation operation with K operands, with K integer greater than or equal to 2, comprises, in addition to the actual calculation steps , K successive reading steps in the memory to read the K operands to be processed, and a possible step of rewriting the result of the operation in the memory. In the embodiment of FIG. 2, the execution of a logical calculation operation with K operands can be carried out in a time as short as the time required to implement a single read cycle in the memory . The result of the operation can be read out of the memory, and / or rewritten in the memory during a subsequent write operation.
    It will be further noted that in the embodiment of FIG. 2, several logical operations of different natures can be carried out in parallel on the same column of the memory (the OR, NO OR, AND, NAND and EXCLUSIVE OR operations in FIG. example described above).
    In the example of FIG. 2, in each column of the memory circuit, the conductive track VGNDT of the column is connected to the ground (GND) via a transistor 22, and the conductive track VGNDF is connected to the GND by means of a transistor 24. The transistor 22 has its gate connected to a PCHT control node via an inverter 26, and the transistor 24 has its gate connected to a control node PCHF via an inverter 28. In this example, the transistors 22 and 24 are N-channel MOS transistors. The PCHT and PCHF nodes are set low by the control circuit 14 during read operations. and / or logical calculation so as to bring the conductive tracks VGNDT and VGNDF to a low level and allow, if appropriate (depending on the values of the data contained in the selected cells), the discharge of the conductive tracks RBLT and RBLF. Apart from the reading and / or logical calculation operations, the PCHT and PCHF nodes are kept at a high level so as to limit the leakage currents via the read ports. In particular, when one or more lines are activated during a read and / or logical calculation operation, the PCHT and PCHF nodes of the columns not selected for the operation are kept at a high level.
    FIG. 3 schematically represents an alternative embodiment of the memory circuit of FIG. 2.
    The memory circuit of FIG. 3 differs from the memory circuit of FIG. 2 mainly in that, in the circuit of FIG. 3, in each column of the matrix, the inverters 26 and 28 and the transistors 22 and 24 are replaced by other control elements of VGNDT and VGNDF reference conductor tracks of the column. More particularly, in the example of FIG. 3, the memory circuit comprises, for each column of the memory, an AND logic gate 31, an OR logic gate 33, and four inverters 35, 36, 37 and 38. The logic gate AND 31 has a first input connected to an application node of a first control bit signal VGNDHIGH through the inverter 35, and a second input connected to an application node of a second binary signal of control COMP_OP via the inverter 36. Thus, the logic gate ET receives, on its first input, the complementary VGNDHIGH of the signal VGNDHIGH, and on its second input, the complementary COMP_OP of the signal COMP_OP. The first input of the AND logic gate 31, or output of the inverter 35, is further connected to the reference conductor track VGNDT of the column via the inverter 37. Thus, the conductive track VGNDT is maintained to a high state when the VGNDHIGH bit signal is in the high state, and to a low state when the VGNDHIGH bit signal is low. The OR logic gate 33 has a first input connected to the output conductive track RBLT of the column, and a second input connected to the output of the AND logic gate 31. The output of the OR logic gate 33 is connected to the conductive track The VGNDF conductive track is maintained in a high state when the output of the OR gate 33 is low, and in a low state when the output of the OR gate 33 is low. the output of the OR logic gate 33 is high.
    The memory circuit of FIG. 3 makes it possible to carry out the same basic logic operations as the circuit of FIG. 2. For this, the control circuit 14 keeps the signals VGNDHIGH and COMP_OP in the low state in the column or columns concerned by a read operation or logical calculation. As a result, the reference conductive tracks VGNDT and VGNDF of the column or columns concerned by the operation are maintained at a low potential, which makes it possible, as the case may be (as a function of the values of the data contained in the selected cells), the discharge of the conductive tracks RBLT and RBLF.
    The memory circuit of FIG. 3 furthermore makes it possible to perform compound logical operations. For this, the circuit 14 keeps the signals VGNDHIGH and COMP_OP high in each column concerned by the operation. As a result, the reference conductor track VGNDT of the column is maintained at a high potential. In addition, the output of the AND logic gate 31 is low, so that the state, high or low, of the output of the OR logic gate 33 is set by the level, high or low, of the conductive output track RBLT of the column. Thus, the column reference conductor VGNDF of the column is kept low when the output conductive track RBLT of the column is in the high state, and is kept high when the output conducting track RBLT of the column is in the low state.
    The control circuit 14 then activates simultaneously reading two elementary cells of the column, the cells 10-L ^ j and in the example shown. One of the two cells, the cell 10 in this example, is activated via its RPT read port, the control circuit 14 maintaining the RPF read port of this blocked cell. The other cell, the cell in this example, is activated via its RPF read port, the control circuit 14 holding the RRT reading port of this blocked cell.
    Following the activation of the read port RPT of the cell 10j_ ^ j, the output conductive track RBLT of the column is in a state corresponding to the complementary bit value A of the binary value A stored on the storage node BLTI of Cell 10. The value A is thus transferred to the conductive track VGNDF via the OR logic gate 33 and the inverter 38. The final level read on the output track RBLF of the column at the end of the read operation then corresponds to the result ÆB of a compound logical operation. In addition, the inverted output RBLF of the column, i.e., the output node of the inverter 18, provides a signal corresponding to the result A + B of the inverse composite logic operation.
    Although an example of implementation of a logical operation composed of two operands has been described here, logical operations composed of more than two operands can be implemented in a similar manner, while simultaneously activating a higher number of read operations. two cells of the same column. Each activated cell is activated via only one of its RPT and RPF read ports, with at least one cell being activated via its RPT port and at least one cell being activated via its RPF port. In addition, compound logic operations can be implemented on words of several bits by simultaneously activating several columns of the circuit.
    The memory circuits of FIGS. 2 and 3 also make it possible to carry out operations of the majority type, making it possible to determine whether a column of the matrix or a portion of a column of the matrix contains a majority of 1 or a majority of 0. For this, the control circuit 14 activates simultaneously, for each elementary cell of the column or the portion of column concerned by the operation, the two read ports RPT and RPF of the cell, after having preloaded at a high level the tracks RBLT and RBLF output conductors of the column and, keeping the reference conductive tracks VGNDT and VGNDF of the column at a low level. After a predetermined fixed discharge time, the sign of the voltage difference ΔΥ = Vrblt ~ Vrblf between the conductive tracks RBLT and RBLF of the column is determined. When the column or activated column portion contains a majority of 1, the RBLT output track discharges faster than the RBLF output track, and the AV voltage is negative at the end of the set discharge time. If, on the other hand, the activated column or column portion contains a majority of 0, the output track RBLF discharges faster than the output track RBLT, and the voltage Δν is positive at the end of the set discharge time. The sign taken by the voltage AV at the end of the predetermined discharge time thus makes it possible to know if the column or the portion of column activated contains a majority of 1 or a majority of 0. The sign of the voltage AV can be determined by means of an output amplifier, not shown, for example arranged at the foot of the column, adapted to amplify the voltage difference AV = Vrblt ~ Vrblf ^ t to provide a binary signal representative of the sign of this difference.
    FIG. 4 schematically represents another alternative embodiment of a memory circuit adapted to implementing calculation operations.
    The memory circuit of FIG. 4 comprises, for example, the same elements as the memory circuit of FIG. 2 or 3, arranged in substantially the same manner, and furthermore comprises additional circuit elements making it possible to implement arithmetic calculation operations. .
    More particularly, the circuit of FIG. 4 comprises, for each column of the matrix, in addition to the elements described in relation to FIGS. 2 and 3, two NAND gates 41 and 43 forming with the NOR gate of the column, a half-adder. In each column of rank j of the matrix, with the exception of the first column (j = 1), the gate 41 has a first input connected to the output conductive track RBLF of the column of previous rank (j-1) and a second input connected to the output of the NOR gate 20 of the rank column j. The gate 41 of the rank column j = the first input connected to an application node of a low level signal (binary value 0), and a second input connected to the output of the NOR gate 20 of the rank column j = l. Each NAND gate 41 further has a second input connected to the output of the NOR gate 20 of the column to which it belongs. Each NAND gate 43 has a first input connected to the output conductor track RBLF of the column to which it belongs, and a second input connected to the output of the NAND gate 41 of the column to which it belongs.
    In the example of Figure 4, only the first three columns C] _, Cg / Cg of the matrix have been represented. In addition, these columns were not detailed. In particular, in FIG. 4, the elementary cells present in each column are not detailed. Only the output conductive tracks RBLT and RBLF of each column, as well as the logic gates 20, 41 and 43 associated with each column, are detailed. In addition, the control circuit 14 of the memory circuit has not been shown in FIG. 4.
    The operation of an addition operation to two operands of two bits AqA] _ and BqB] ^ will now be described in relation to FIG. 4. The two bits Aq and A] ^ of the first operand are stored in two dots. a same first line of the memory, respectively in the column Cg and in the column C3 in the example shown, and the two bits Bq and B] _ of the second operand are stored in two cells of the same second line of the memory, in the same columns as the bits Aq and A] _ respectively, that is to say in columns C2 and C3 in this example. The execution time of the addition operation corresponds to the time required to implement three read cycles in the memory.
    During a first cycle, the control circuit 14 is controlled identically or similarly to what has been described with reference to FIG. 2, to activate simultaneously in reading, via the two read ports RPT and RPF, the two lines of the memory circuit respectively containing the bits Aq and A] _ and the bits Bq and B] _, after having preloaded high the output tracks RBLT and RBLF columns Cg and C3, and passed transistors 22 and 24 (not visible in Figure 4) columns Cg and C3. At the end of the first cycle, the output signal Sj_Q of the NOR gate of the column Cg corresponds to the result of an EXCLUSIVE OR operation between the bits Aq and Bq, and the output signal Sj_] _ of the gate NO OR 20 of column C3 corresponds to the result of an EXCLUSIVE OR operation between bits A] ^ and B] ^. The signals S ^ and S ^^ ^ correspond to the results, in each column, of the sum, without restraint, of the values Aq and Bq, respectively A] ^ and B] ^. The signal present on the output track RBLF of the column Ci corresponds to the half-adder input restraint Cl ^ O of the column Cg, and the signal present on the output track RBLF of the column C3 corresponds to the hold of input of the half-adder of column C3. The output signal of the NAND gate 43 of the column C 1 corresponds to the half-adder output hold C 1 0 L of the column C 1, the output signal of the NAND gate 43 of the column C g corresponds to the output hold. Half-adder Coutl of column Cg, and the output signal of NAND gate 43 of column C3 corresponds to the Cout2 output half-adder output of column C3. At the end of the first cycle, the values Sj_Q and are respectively written in the columns Cg and C3, in a same line of the memory circuit distinct from the lines containing the values Aq, A] _ and Bq, B] _.
    During a second cycle consecutive to the first cycle, the output conductive tracks RBLT and RBLF are not reloaded to a high level, so that the values of the retentions ^ inO '^ outO' ^ out1 '' ^ out2 remain preserved. In the second cycle, CoutO Coutl output deductions available respectively on the output node of gate 43 of column C] and on the output node of gate 43 of column Cg are respectively written in the column. Cg and in the column C3, in a same line of the memory circuit different from the lines containing the values Aq, A] _, Bq, B] _ and Sj_q,
    During a third cycle consecutive to the second cycle, the control circuit 14 is again controlled in the same way or similar to that described in connection with FIG. 2, to activate simultaneously in reading, via the two reading ports. RPT and RPF, the two lines of the memory circuit respectively containing the bits Sj_Q and and the CquLO Coutl 'bits after having preloaded high the output tracks RBLT and RBLF columns C2 and C3, and passed transistors 22 and 24 (not visible in Figure 4) columns Cg and C3. At the end of the third cycle, the output signal SO of the NOR gate 20 of the column C2 corresponds to the result of an EXCLUSIVE OR operation between the bits S ^ q and CoutO 'the signal SI of the output of the gate NO OR Column C3 corresponds to the result of an EXCLUSIVE OR operation between the bits S 1 and C 1 and signals S0 and S1 respectively correspond to the most significant bit and the least significant bit of the final result of the addition. The signal available on the output node of the NAND gate 43 of column C3 corresponds to the final value Cost retaining the addition.
    Subtractions can be carried out in a similar way but with an additional cycle, because the value of the deductions then no longer corresponds to an AND, as in the case of addition, but to a compound logical operation of type A.B.
    Increment or decrement operations may further be implemented using the addition / subtraction circuits described above.
    Figure 5 schematically shows a particularly advantageous example of a memory circuit according to one embodiment.
    The memory circuit of FIG. 5 differs from the memory circuit of FIG. 2 mainly in that, in the circuit of FIG. 5, in each column of the matrix, the inverters 16 and 18 and the NOR gate 20 are replaced by a logic circuit 500.
    The logic circuit 500 comprises three inverters 51, 52 and 53, three NAND logic gates 54, 55 and 56, and a multiplexer 57 with two binary inputs and a data bit output. The inverter 51 has its input connected to the output conductive track RBLT of the column and the inverter 52 has its input connected to the output conductive track RBLF of the column. The multiplexer 57 has a first data input (0) connected to the input of the inverter 51, and a second data input (1) connected to the output of the inverter 51. The output of the multiplexer 57 is connected to the input of the inverter 53 and a first input of the NAND gate 54. The multiplexer 57 further comprises an ADD control input for selecting the data input (0) or (1) of the multiplexer to reproduce. on its way out. The second input of the NAND gate 54 is connected to the input of the inverter 52. The output of the inverter 52 is connected to a first input of the NAND gate 55 and the output of the inverter 53 is connected. at the second input of the NAND gate 55. The output of the NAND gate 54 is connected to a first input of the NAND gate 56, and the output of the NAND gate 55 is connected to the second gate entrance. NO AND 56.
    In the example shown, the reference conductor tracks VGNDT and VGNDF of the column are directly connected to ground (GND). As a variant, the reference conductive tracks VGNDT and VGNDF may be connected to ground via transistors 22 and 24 as described with reference to FIG. 2.
    The control circuit 14 (CTRL) is adapted to control the memory circuit to implement conventional read operations of the type described in relation to FIG. 1, or to implement write operations via the conductive tracks of FIG. write access WBLT, WBLF, and WWL cells.
    The control circuit 14 is further adapted to control the memory circuit for implementing a certain number of basic logic operations directly in the memory, without having to pass the data through a unit external to the circuit.
    For this purpose, the control circuit 14 is adapted to activate simultaneously two or more than two readings of elementary cells of the same column of the circuit, via the access ports RPT, and / or via the ports d RPF access of these cells. By way of illustrative example, it is considered that the two cells 10 and 10 shown in FIG. 5 are activated simultaneously in read mode, one (the cell 10 1) via its single port RPT, and the other (the 10j_ ^ j + cell) via its single RPF port. For this, after having preloaded at a high level the conductive output tracks RBLT and RBLF of the column and set the reference conductive tracks VGNDT and VGNDF of the column at a low level, the selection transistor T4 of the cell 10i, j and the selection transistor T6 of the cell 10 is simultaneously turned on by the control circuit 14, the selection transistors T6 of the cell 10 and T4 of the cell 10 i being kept off. A denotes the binary value stored on the BLTI node of the cell 10 and j, and B the binary value stored on the BLTI node of the cell 10i + i, j. The cell 10i then stores on its node BLFI the complement A of the value A, and the cell 10j + stores on its node BLFI the complementary B of the value B. Following the activation of the cell 10f , j via its port RPT and cell 10i, j + i via its port RPF, the value A can be read on the output track RBLT of the column and the value B can be read on the output track RBLF of the column. The values A and B can be read respectively on the output nodes of the inverters 51 and 52. According to a first mode of operation, the multiplexer 57 is controlled by the control circuit 14, via its control input ADD, to connect its first data input (0) at its output. The value ÂB can then be read on the output node of the NAND gate 54, and the value AB can be read on the output node of the NAND gate 55. The value on the output node of the NAND gate 56 corresponds to the result XOR (A, B) of an EXCLUSIVE OR operation between the values A and B. According to a second mode of operation, the multiplexer 57 is controlled by the control circuit 14 to connect its second data input (1 ) at its output. The value AB can then be read on the output node of the NAND gate 54, and the value AB (that is, A OR B) can be read on the output node of the NAND gate. 55. The value on the output node of the NAND gate 56 corresponds to the result NXOR (A, B) of an EXCLUSIVE OR operation complemented between the values A and B. Alternatively, it is considered that the two cells 10j_ 10 and 10 shown in FIG. 5 are simultaneously activated for reading via their two read ports RPT and RPF. For this, after having preloaded the output conductive tracks RBLT and RBLF of the column at a high level and set the reference conductive tracks VGNDT and VGNDF of the column at a low level, the selection transistors T4 and T6 of the cell 10j_ and the selection transistors T4 and T6 of the cell 10i are simultaneously turned on by the control circuit 14. Following the activation of the cell 10i via its ports RPT and RPF and the cell 10j_ ^ j +] _ via its RPT and RPF ports, the value A + B (NOR logical operation) can be read on the output track RBLT of the column and the value AB (logical operation AND) can be read on the RBLF output track of the column. The values A + B (OR logic operation) and AB (NAND logic operation) can be read respectively on the output nodes of the inverters 51 and 52. According to a third mode of operation, the multiplexer 57 is controlled by the control circuit. 14 to connect its first data input (0) to its output. The value NXOR (A, B) can then be read on the output node of the NAND gate 55, and the value XOR (A, B) can be read on the output node of the NAND gate 56. According to a fourth mode of operation, the multiplexer 57 is controlled by the control circuit 14 to connect its second data input (1) to its output. The value AB can then be read on the output node of the NAND logic gate 54, the value A + B can be read on the output node of the NAND logic gate 55, and the value NXOR (A, B). can be read on the output node of the NAND gate 56.
    By simultaneously activating in read mode a number greater than two of cells of the same column, the aforementioned logic operations can be implemented with a number of operands greater than 2. Moreover, by simultaneously activating several columns of the circuit in readings, these logical operations can be implemented on words of several bits.
    FIG. 6 schematically represents a particularly advantageous variant embodiment of the memory circuit of FIG. 5.
    The memory circuit of FIG. 6 comprises the same elements as the memory circuit of FIG. 5, arranged substantially in the same way, and differs from the memory circuit of FIG. 5 in that, in the memory circuit of FIG. each column of the matrix, the logic circuit 500 comprises additional elements adapted to the implementation of arithmetic operations. More particularly, in the example of FIG. 6, in each column of the matrix, the logic circuit 500 further comprises a latch 61, for example a D flip-flop, the input of which is connected to the output node of FIG. the NAND gate 54 and whose output is connected to the first input of the NAND gate 56 and the NAND gate 65, and a flip-flop 62, for example a flip-flop D, the input of which is connected to the output node of the NAND gate 55 and whose output is connected to the second input of the NAND gate 56. The circuit 500 further comprises a multiplexer 63 with two binary inputs and a binary output. The multiplexer 63 has a first data input (0) connected to the output of the NAND logic gate 56, and a second data input (1) connected to an inverted output of the NAND logic gate 56. The circuit 500 comprises furthermore, a NAND logic gate 64 whose first input is connected to the output of the multiplexer 63 and whose second input is connected to a node Cjjj. The multiplexer 63 further comprises an ADD control input for selecting the data input (0) or (1) of the multiplexer to be reproduced on its output. The circuit 500 further comprises a NAND logic gate 65, a first input of which is connected to the output of the NAND gate 64, and the second input of which is connected to a node connected to the output of the flip-flop 61. The output of FIG. the NAND logic gate 65 is connected to a cost circuit node 500. The circuit 500 further comprises a flip-flop 66, for example a flip-flop D, whose input is connected to the node and a flip-flop 67, for example a flip-flop D, whose input is connected to the output node of the multiplexer 63. The circuit 500 further comprises an EXCLUSIVE OR logic gate 68, a first input of which is connected to the output of the flip-flop 66 and whose second input is connected to the output of FIG. the flip-flop 67. The output of the EXCLUSIVE OR gate 68 is connected to a node S of the circuit 500.
    In the memory circuit of FIG. 6, the circuits 500 of several columns of the matrix, for example neighboring columns of the matrix, are connected in a chain via their nodes Cju and C to form an add / add circuit. substraction. By way of example, it is considered that the circuits 500 of Q distinct columns of the matrix are connected in a chain to form a Q-bit operand addition / subtraction circuit. Hereinafter denoted by 500}, the circuit of the k-th column of the set of Q columns forming the addition-subtraction circuit, with k integer ranging from 1 to Q and Q integer less than or equal to N ( N denoting the number of columns of the matrix). In this example, the low rank k columns of the addition / subtraction circuit correspond to the low order bits of the addition / subtraction circuit, and the high rank columns of the addition / subtraction circuit correspond to the weight bits. strong of the addition / subtraction circuit. With the exception of the circuit 500], each circuit 500}. of the addition / subtraction circuit at its node Cjj ^ connected to the node Cost circuit of previous rank 500} ._] ^. The addition / subtraction circuit further comprises an additional output flip-flop (not shown) whose input is connected to the node Cqut circuit 500q.
    The flow of an addition operation to two Q-bit operands each will now be described. The Q bits Af, A2, ..., A}., .. .Aq (from the least significant bit to the most significant bit) of the first operand are stored in the same first line of rank 11 of the memory, respectively in Q columns of rank 1 to Q defining the addition / subtraction circuit. The Q bits B] _, B2, ..., B}., ... Bq (from the least significant bit to the most significant bit) of the second operand are stored in the same second rank row 12 of the memory, respectively in Q columns of rank 1 to Q of the memory defining the addition / subtraction circuit. In the example that will be described, the execution time of the addition operation corresponds to the time required to implement three read cycles in the memory. The described embodiments are however not limited to this particular case.
    During the addition operation, the control circuit 14 applies a low level potential corresponding to the binary value '0', for example the potential GND, on the node Cju of the circuit 500] _ of the addition / subtraction circuit. . In addition, the control circuit 14 controls the multiplexer 57 to connect its second data input (1) to its output, and the multiplexer 63 to connect its second data input (1) to its output.
    During a first cycle, the control circuit 14 is controlled to activate simultaneously in reading the two rows of rank 11 and 12 of the memory, one (the line of rank II) via its only read ports RPT, and the other (the line of rank i2) via its only RPF read ports. At the end of the first cycle, in each column of rank k of the addition / subtraction circuit, the flip-flop 61 of the circuit 500] stores the value corresponding to the complement of the local hold of rank k of the addition; that is to say the retention of the bitwise addition of the values and B} ,. In addition, at the end of the first cycle, flip-flop 62 of circuit 500} stores the value
    During a second cycle consecutive to the first cycle, the values stored in the flip-flops 61 and 62 are transmitted on the output nodes of these flip-flops. In each row column k of the addition / subtraction circuit, the value on the output node of the multiplexer 63 is then equal to XOR (A} -, B} -), that is to say, to the result of the bitwise addition of the values A} - and B} -. At the end of the second cycle, this value is stored in the flip-flop 67. In addition, during the second cycle, the local deductions of the addition are propagated by the NAND gates 64 and 65, and in each column of rank k of the addition / subtraction circuit, the flip-flop 66 of the circuit 500} stores the propagated local retention value applied to its node Cjjg. At the end of the second cycle, the value of the circuit cost node 500q, corresponding to the final value of the hold of the addition, is stored in the additional flip-flop (not shown) associated with the circuit 500q.
    During a third cycle consecutive to the second cycle, the values stored in the flip-flops 66 and 67 are transmitted on the output nodes of these flip-flops. The result of the addition then corresponds to the word of Q bits formed by the Q binary values provided on the output nodes S of the circuits 500} - of the addition / subtraction circuit, to which is added the retaining bit stored in the additional flip-flop (not shown) associated with the circuit 500q.
    The progress of a subtraction operation of two Q-bit operands is similar to the progress of an addition operation, except that, during a subtraction operation, the control circuit 14 applies a corresponding high level potential. to the binary value '1', for example the potential VDD, on the node Cjj ^ of the circuit 500] ^ of the addition / subtraction circuit. In addition, during the subtraction operation, the control circuit 14 controls the multiplexer 57 to connect its first data input (0) to its output, and the multiplexer 63 to connect its first data input (0) to its output .
    It should be noted that in the example of FIG. 6, the multiplexers 57 and 63 can be controlled by the same control signal supplied by the control circuit 14.
    FIG. 7 schematically represents another variant embodiment of the memory circuit of FIG. 5.
    The memory circuit of FIG. 7 comprises the same elements as the memory circuit of FIG. 5, arranged in substantially the same manner, and differs from the memory circuit of FIG. 5 in that, in the memory circuit of FIG. each column of the matrix, the logic circuit 500 comprises additional elements suitable for the implementation of comparison operations. More particularly, in the example of FIG. 7, in each column of the matrix, the logic circuit 500 further comprises a flip-flop 71, for example a flip-flop D, the input of which is connected to the output node of the NO gate. AND 54 and whose output is connected to the first input of the NAND gate 56, and a flip-flop 72, for example a flip-flop D, the input of which is connected to the output node of the NAND gate 55 and whose output is connected to the second input of the NAND gate 56. The circuit 500 further comprises a NOR logic gate 73 whose first input is connected, via an inverter, to a node connected to the output of the NAND gate. flip-flop 72, and whose second input is connected to a node GTj] ^. The circuit 500 further comprises a NOR logic gate 74 whose first input is connected, via an inverter, to a node ΙΤι, ι ^ connected to the output of the flip-flop 71, and whose second input is connected to a node LTjj ^. The circuit 500 further comprises an inverter 75 whose input is connected to the output of the NOR gate 73 and whose output is connected to a node GTquT 'and an inverter 76 whose input is connected to the output of the gate NO OR 74 and whose output is connected to a node LTqut · circuit 500 further comprises a NOR gate 77, a first input of which is connected to the output of the NOR gate 73 and whose second input is connected to the node LTqut a NOR gate 78 whose first input is connected to the output of the NOR gate 74 and the second input of which is connected to the node GTQUX · The circuit 500 further comprises a flip-flop 79, for example a flip-flop D, whose the input is connected to the output of the NOR gate 77, and a flip-flop 80, for example a flip-flop D, the input of which is connected to the output of the NOR gate 78. In this example, the circuit 500 comprises plus a transistor 81 whose gate is connected to the output of the flip-flop 79, and n transistor 82 whose gate is connected to the output of flip-flop 80. Transistor 81 has a first conduction node connected to an output node if circuit 500 and a second grounded conduction node (GND), and the transistor 82 has a first conduction node connected to an output node s2 of the circuit 500 and a second conduction node connected to ground (GND). In the example shown, the second conduction node of the transistor 81 is connected to ground via a transistor 83, and the second conduction node of the transistor 82 is connected to the ground via a transistor. transistor 84. In the example shown, the transistors 81, 82, 83, 84 are N channel MOS transistors. In addition, in this example, the transistors 83 and 84 have their gates connected to the same application node. a PCH control signal.
    In the memory circuit of FIG. 7, the circuits 500 of several columns of the matrix, for example neighboring columns of the matrix, are connected in a chain via their nodes GTjjj, GTqut LTjj ^, LTqtjt POur to form a circuit comparison. By way of example, it is considered that the circuits 500 of R distinct columns of the matrix are connected in a chain to form an R-bit operand comparison circuit. The circuit of the 1-th column of the set of R columns forming the comparison circuit is denoted hereinafter, with 1 integer ranging from 1 to R and R being less than or equal to N (N denoting the number of columns in the matrix). In this example, the low rank 1 columns of the comparison circuit correspond to the most significant bits of the comparison circuit, and the high rank 1 columns of the comparison circuit correspond to the least significant bits of the comparison circuit. With the exception of the circuit 500], each circuit 500] _ of the comparison circuit has its node GTjj ^ connected to the node GTqut previous rank circuit 500] __] ^, and has its node LTju connected to the node LTqut of the circuit. previous rank 500g _] ^. The output nodes if R circuits 500] _ of the comparison circuit are connected to the same first conductive output track Isl of the comparison circuit, and the output nodes s2 of the R circuits 500g of the comparison circuit are connected to the same second conductive output track ls2 of the comparison circuit. The comparison circuit further comprises a flip-flop 85, for example a flip-flop D, whose input is connected to the conductive track Is1, and a flip-flop 86, for example a flip-flop D, whose input is connected to the conductive track. ls2. The comparison circuit further comprises an inverter 87 whose input is connected to the output of the flip-flop 85, and an inverter 88 whose input is connected to the output of the flip-flop 86. In this example, the comparison circuit further comprises an OR gate 89 whose first input is connected to the output of the flip-flop 85 and whose second input is connected to the output of the flip-flop 86. The output of the inverter 87 is connected to a node LT, the output of inverter 88 is connected to a node GT, and the output of OR gate 89 is connected to an EQ node. The comparison circuit furthermore comprises a transistor 90 connecting via its conduction nodes. the conductive track Isl at an application node of a high reference potential, for example the high supply potential VDD, and a transistor 91 connecting, via its conduction nodes, the conductive track ls2 to the node VDD. Transistors 90 and 91 have their gates connected to the same application node of a control signal. In this example, the transistors 90 and 91 are P-channel MOS transistors and have their gates connected to the same PCH control node as the transistors 83 and 84.
    The progress of a comparison operation with two operands of R-bits each will now be described. The R bits Al, A2, ..., Al,. . .Ar (from the most significant bit to the least significant bit) of the first operand are stored in the same first line of rank 11 of the memory, respectively in the R columns of rank 1 to R defining the comparison circuit . The R bits Bi, Bg,..., Bq, .bji (from the most significant bit to the least significant bit) of the second operand are stored in the same second line of rank i2 of the memory, respectively in the R columns of rank 1 to R of the memory defining the comparison circuit. In the example that will be described, the execution time of the comparison operation corresponds to the time required to implement three read cycles in the memory. The described embodiments are however not limited to this particular case. In particular, as an alternative, the second and third cycles can be confused.
    During the comparison operation, the control circuit 14 applies a low level potential corresponding to the binary value '0', for example the potential GND, on the nodes and LTj] ^ of the circuit 500] _ of the comparison circuit. In addition, the control circuit 14 controls the multiplexer 57 to connect its first data input (0) to its output.
    During a first cycle, the control circuit 14 is controlled to activate simultaneously in reading the two rows of rank 11 and 12 of the memory, one (the line of rank II) via its only read ports RPT, and the other (the line of rank i2) via its only RPF read ports. At the end of the first cycle, in each row 1 column of the comparison circuit, the flip-flop 71 of the circuit 500] _ stores the value Ai-Bi corresponding to the result complemented by the local comparison operation A] _ <B] _ . In addition, the flip-flop 72 stores the value Ai.Bi corresponding to the result complemented by the local comparison operation A] _> B] _.
    During a second cycle consecutive to the first cycle, the values stored in the latches 71 and 72 are transmitted on the output nodes of these latches. At the end of the second cycle, the output values of the NOR gates 77 and 78 are stored in latches 79 and 80 respectively.
    Prior to a third consecutive cycle in the second cycle, the transistors 90 and 91 are turned on and then blocked, so as to preload the conductive tracks Isl and ls2 to a high level. In addition, the transistors 83 and 84 are turned on and then off, so as to preload at a low level the common conduction node between the transistors 81 and 83, and the common conduction node between the transistors 82 and 84.
    During the third cycle, the values stored in the latches 79 and 80 are transmitted on the output nodes of these latches. At the end of the third cycle, the state of the output conductive tracks Is1 and ls2 is representative of the final result of the comparison. In this example, during the third cycle, the level of the conductive track Is1 is stored in the flip-flop 85, and the level of the conductive track ls2 is stored in the flip-flop 86. The state of the output node LT of the comparison circuit then corresponds to the result of the comparison operation A] _A2. . .AT]_. . .Ap ^ <B] _B2. . .B] _. . .Br. The state of the output node GT of the comparison circuit corresponds to the result of the comparison operation A; l- ^ 2 · · - ^ l · · -¾> B2B2. . .B ^. . .Br. The state of the output node EQ of the comparison circuit corresponds to the result of the comparison operation A] _A2. . .AT]_. . .Ar = B] _B2. . .B] _. . .Br.
    It will be noted that the variant embodiments of FIGS. 6 and 7 can be combined. In this case, the flip-flops 71 of FIG. 7 and 61 of FIG. 6 can be merged, and the flip-flops 72 of FIG. 7 and 62 of FIG. 6 can be combined.
    It will furthermore be noted that the addition / subtraction operations described with reference to FIG. 6, and / or the comparison operations described with reference to FIG. 7, can be processed in a pipeline so as to be able to generate a result of FIG. operation per cycle. Alternatively, the memory circuits described in connection with Figures 2, 3 and 4, 5, 6 and 7 may further comprise circuit elements (not shown) for implementing shift operations. For this, the memory circuit may comprise, for each column Cj, a controllable multiplexer for connecting the output conductive track RBLT of the column Cj to the write circuit (conducting track WBLT) of the same column C j, so as to implementing a conventional read-rewrite operation, ie the write circuit of the column Cj +] ^ of next rank, so as to implement an offset operation.
    Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the embodiments are not limited to the particular example of an elementary cell described with reference to FIG. 1. More generally, the embodiments described can be adapted to other types of elementary memory cells, volatile or nonvolatile, at one or more read ports.
    FIG. 8 is a circuit diagram of an example of a non-volatile elementary memory cell with a single reading port, which can be used as a base cell of a memory circuit adapted to implementing calculation operations.
    The elementary cell of FIG. 8 is a resistive memory cell. This cell comprises a storage cell with two programmable resistive resistor elements R1 and R2, and a transistor 101. The elements R1 and R2 are connected in series between an XLT node and an XLF node of the cell. The midpoint between the elements R1 and R2 defines a data storage node of the cell. The transistor 101 is a write access transistor, connecting, via its conduction nodes, the midpoint between the elements R1 and R2 to a write node BL of the cell. The gate of transistor 101 is connected to a control node WL of the cell. The elementary cell of FIG. 8 further comprises a read port RPT with two transistors 103 and 105. The transistors 103 and 105 are connected in series via their conduction nodes between an output conducting track NL of the cell and a node GND. applying a reference potential of the cell. The transistor 105 is located on the GND node side and at its gate connected to the midpoint between the resistive elements R1 and R2. Transistor 103 is located on the conductive track side NL and has its gate connected to a conductive read control track SL. In this example, the transistors 101, 103 and 105 are N-channel MOS transistors.
    A memory circuit according to one embodiment may comprise a plurality of elementary cells of the type described in relation to FIG. 8, identical or similar, arranged in a matrix according to rows and columns. The cells of the same line are interconnected via their conductive tracks SL, respectively WF, and the cells of the same column are interconnected via their conductive paths BL, respectively XLT, respectively XLF, respectively NL.
    To perform a reading of an elementary cell of the memory via its read port RPT, the output conductive track NL of the cell is precharged to a high level, for example to the power supply voltage λ / DD of the circuit. The transistor 103 of the cell is then turned on by applying a high level signal on the conductive track SL of the cell. After the activation of the transistor 103, the conducting track RBLT is discharged if the potential of the storage node (midpoint between the resistors R1 and R2) is at a high level (passing transistor 105), and remains substantially at its precharging level. if the potential of the storage node is at a low level (transistor 105 blocked). The reading of the potential of the RBLT track via a not shown reading circuit, for example arranged at the bottom of the column, makes it possible to determine the value of the data bit stored in the elementary cell.
    In a manner similar to that described with reference to FIGS. 2, 3, 4, 5, 6 and 7, the memory of FIG. 8 may comprise a control circuit (not shown) adapted to control the memory to implement calculation operations. For this purpose, the control circuit is, for example, adapted to activate simultaneously two or more than two readings of elementary cells of the same column of the circuit, via the access ports RPT of these cells, after having preloaded at a high level the output track NL of the column.
    More generally, the embodiments described can be adapted to any type of elementary memory cell comprising at least one storage node of a data bit, and at least one read port comprising a read transistor connected by its gate to the node. storage, and a selection transistor connected in series with the read transistor between an application node of a reference potential of the cell and an output conductive track common to all the elementary cells of the same column of the memory .
    The described embodiments preferably apply to differential cells whose two read ports are individually controllable. As a variant, the embodiments described can be adapted to elementary cells having a number of read ports greater than two, which has the advantage of increasing the number and the complexity of the logical and / or arithmetic calculation operations. that can be implemented.
    权利要求:
    Claims (14)
    [1" id="c-fr-0001]
    A memory circuit adapted to implement calculation operations, this circuit comprising: a plurality of elementary memory cells arranged along lines and columns, each cell comprising: a first storage node (BLTI) a data bit, - a first read transistor (T3) connected by its gate to said first storage node (BLTI), and - a first selection transistor (T4) connected in series with the first read transistor (T3 ) between a first node (VGNDT) for applying a reference potential of the cell and a first conductive output track (RBLT) common to all the cells of the same column of the circuit; and a control circuit (14) configured to simultaneously activate the first selection transistors (T4) of at least two cells (10j_ ^ j, 10j _ +] _ ^ j) of the same column of the circuit, and to read on the first output conductive track (RBLT) of the column represents a value representative of the result of a first logical operation whose operands are the data stored in the at least two cells (10j, 10j, + 1, j).
    [2" id="c-fr-0002]
    The memory circuit of claim 1, further comprising, for each column of the circuit, a first inverter (16; 51) having an input node connected to the first output conductor track (RBLT) of the column.
    [3" id="c-fr-0003]
    3. Memory circuit according to claim 1 or 2, wherein each elementary cell further comprises: a second node (BLFI) for storing a bit of data complementary to the bit stored on the first storage node (BLTI) of the cell, - a second reading transistor (T5) connected by its gate to said second storage node (BLFI), and - a second selection transistor (T6) connected in series with the second reading transistor (T5) between a second node (VGNDF) applying a reference potential of the cell and a second conductive output track (RBLF) common to all the cells of the same column of the circuit, the control circuit (14) being further configured to simultaneously activate the second selection transistors (T6) of at least two cells (10j_ ^ j, 10j _ +] _ ^ j) of the same column of the circuit, and to read on the second output conducting track (RBLF) of the column a representative value of the result and a second logical operation whose operands are the data stored in said at least two cells (10-, 10-, 10-).
    [4" id="c-fr-0004]
    A memory circuit according to claim 3, wherein the control circuit (14) is further configured to simultaneously activate: the first (T4) and second (T6) two-cell selection transistors (10j_ ^ j, 10j_ +) j) of the same column of the circuit; or the first selection transistor (T4) of a first cell (10j_ ^ j) of the circuit and the second selection transistor (T6) of a second cell (10j _ +] _ ^ j) of the same column.
    [5" id="c-fr-0005]
    A memory circuit according to claim 3 or 4, further comprising, for each column of the circuit, a second inverter (18; 52) having an input node connected to the second output conducting track (RBLF) of the column. .
    [6" id="c-fr-0006]
    The memory circuit according to any one of claims 3 to 5, further comprising, for each column of the circuit, a NOR logic gate (20) whose first input is connected to the first output conducting track (RBLT) of the column and a second input is connected to the second output conductor track (RBLF) of the column.
    [7" id="c-fr-0007]
    The memory circuit according to claim 6, further comprising, for each column of the circuit, a first NAND logic gate (41) having a first input connected to an output node of the NOR logic gate (20) of the column, and a second NAND logic gate (43) whose first input is connected to an output node of the first NAND logic gate (41) of the column and a second input of which is connected to the second output conductor track (RBLF) of the column.
    [8" id="c-fr-0008]
    A memory circuit according to claim 6, wherein in each column except the first column of the circuit, the first NAND logic gate (41) has a second input connected to the second output conductor track (RBLF). of a column of previous rank of the circuit.
    [9" id="c-fr-0009]
    The memory circuit according to any of claims 3 to 8, further comprising, for each column: a first reference conductive track interconnecting the first reference potential application nodes (VGNDT) of the column / and a second reference conductive track interconnecting the second nodes (VGNDF) of reference potential application of the column.
    [10" id="c-fr-0010]
    The memory circuit of claim 9, further comprising, for each column: a first reference transistor (22) connecting the first reference conductive track (VGNDT) to a reference node (GND); and a second reference transistor (24) connecting the second reference conductive track (VGNDF) to said reference node (GND).
    [11" id="c-fr-0011]
    The memory circuit of claim 9, further comprising, for each column, an AND gate (31), an OR gate (33), and third (35), fourth (36), fifth (37) and sixth (38) inverters, and wherein: the AND logic gate (31) has a first input connected to an application node of a first control bit signal (VGNDHIGH) via the third inverter (35), and a second input coupled to an application node of a second control bit signal (COMP_OP) via the fourth inverter (36); the output of the third inverter (35) is connected to the first reference conductive track (VGNDT) of the column via the fifth inverter; the OR logic gate (33) has a first input connected to the first output conductor track (RBLT) of the column, and a second input connected to the output of the AND logic gate (31); and the output of the OR logic gate (33) is connected to the second reference conductive track (VGNDF) of the column via the sixth inverter (38).
    [12" id="c-fr-0012]
    The memory circuit according to any one of claims 3 to 5, further comprising, for each column of the circuit: a first multiplexer (57) having a first input connected to the input of the first inverter (51) and a second input connected to the output of the first inverter (51); a third inverter (53) whose input is connected to the output of the first multiplexer (57) / a third NAND gate (54) whose first input is connected to the output of the first multiplexer (57) and whose second input is connected to the input of the second inverter (52); a fourth NAND gate (55) having a first input connected to the output of the third inverter (53) and a second input of which is connected to the output of the second inverter (52); and a fifth NAND gate (56) having a first input connected to the output of the third NAND gate (54) and whose output is connected to the output of the fourth NAND gate (55).
    [13" id="c-fr-0013]
    13. Memory circuit according to any one of claims 1 to 12, wherein said elementary memory cells are volatile memory cells SRAM type.
    [14" id="c-fr-0014]
    14. Memory circuit according to any one of claims 1 to 12, wherein said elementary memory cells are non-volatile resistive memory cells.
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    EP3252774A1|2017-12-06|
    US20170345505A1|2017-11-30|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1654623|2016-05-24|
    FR1654623A|FR3051960B1|2016-05-24|2016-05-24|MEMORY CIRCUIT ADAPTED TO IMPLEMENT CALCULATION OPERATIONS|FR1654623A| FR3051960B1|2016-05-24|2016-05-24|MEMORY CIRCUIT ADAPTED TO IMPLEMENT CALCULATION OPERATIONS|
    EP17172088.1A| EP3252774B1|2016-05-24|2017-05-19|Memory circuit suitable for performing computing operations|
    US15/603,284| US10043581B2|2016-05-24|2017-05-23|Memory circuit capable of implementing calculation operations|
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